SiGe transistor, varactor and p-i-n velocity saturated ballasting element for BiCMOS peripheral circuits and ESD networks

ABSTRACT

An SiGe device configured to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents, wherein for circuit applications, the SiGe device is connected in series with a circuit element for protection of the circuit element. Advantageously, the device may be exploited as a buffer element providing ESD circuit protection for receiver devices, power supply clamp circuits and I/O driver circuits.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to electrostaticdischarge protection and over-current protection of electronic devices,and more specifically, to the use of silicon germanium (SiGe) devicesfunctioning as ESD circuit elements for protecting electronic I/Ocircuits.

[0003] 2. Discussion of the Prior Art

[0004] Electrostatic discharge protection in BiCMOS or CMOS electronicdevices typically utilize resistive elements, e.g., resistors. However,the resistor elements used in BiCMOS or CMOS exhibit linear resistancecharacteristics and do not demonstrate strong velocity saturation (Kirk)effect, i.e., a high resistance state that is significantly above alinear resistance portion of the device's current-voltage curve.Consequently, these types of resistive elements may be suitable forapplications in limited current/voltage ranges and consequently, limitedtypes of ESD and I/O circuit applications.

[0005] It would be highly desirable to provide a device that exhibits astrong velocity saturation effect, i.e., a high dynamic-on resistanceand that may be exploited to provide resistance buffering, and resistorballasting of I/O networks and ESD networks.

[0006] It would additionally be highly desirable to provide a SiGedevice dimensioned to exhibit a strong velocity saturation (Kirk)effect, to provide resistance buffering, and resistor ballasting of I/Onetworks and ESD networks.

SUMMARY OF THE INVENTION

[0007] It is an object of the invention to provide a SiGe transistordevice dimensioned to exhibit a strong velocity saturation (Kirk)effect, and configured to provide resistance buffering, and resistorballasting of I/O networks and ESD networks.

[0008] It is another object of the invention to provide a SiGetransistor in a diodic configuration to provide resistance buffering,and resistor ballasting of I/O networks and ESD networks, utilizing theKirk effect velocity saturation.

[0009] According to the invention, there is provided an SiGe deviceconfigured to exhibit high velocity saturation resistance characteristicfor buffering large voltages at low currents, wherein for circuitapplications, the SiGe device is connected in series with a circuitelement for protection of the circuit element. Advantageously, thedevice may be exploited as a buffer element providing ESD circuitprotection for receiver devices, power supply clamp circuits and I/Odriver circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Further features and advantages of the invention will become morereadily apparent from a consideration of the following detaileddescription set forth with reference to the accompanying drawings, whichspecify and show preferred embodiments of the invention, wherein likeelements are designated by identical references throughout the drawings;and in which:

[0011]FIG. 1 is a chart depicting the current v. voltage characteristicof the diode-configured SiGe npn transistor (and varactor or PIN diode)at various device structure lengths.

[0012]FIGS. 2 and 2A illustrate example differential receiver circuitconfigurations 10, 10′ implementing diode saturation ballasted SiGedevices according to the invention.

[0013]FIG. 3 illustrates an example Bipolar-based ESD power clamp 20implementing SiGe diode velocity saturation ballasting elements 28 a, .. . , 28 n according to the invention.

[0014]FIG. 4 illustrates an example CMOS-based ESD power clamp 30 withvelocity saturation diode ballasting elements 38 a, . . . , 38 n of theinvention.

[0015]FIG. 4A illustrates an example embodiment of a bi-polar powerclamp 30′ as in FIG. 4 with velocity saturation diode ballastingelements 38 a, . . . , 38 n of the invention.

[0016]FIG. 5 illustrates an example receiver circuit 40 including diodesaturation ballasted SiGe devices 48 a, . . . , 48 n according to theinvention.

[0017]FIG. 5A illustrates another example embodiment of a receivercircuit 40′ as in FIG. 5 including another configuration of diodesaturation ballasted SiGe devices 48 a′, . . . , 48 n′ according to theinvention.

[0018]FIG. 6 illustrates an example BiCMOS receiver circuit 50 includinga network of receiver devices 54 a, . . . , 54 n each receiving signalsfrom an input pad 52 through a respective current limiting SiGeheterojunction bipolar transistor (HBT) diode saturation ballast element58 a, . . . , 58 n according to the invention.

[0019]FIG. 6A illustrates another example embodiment of a receivercircuit 50′ as in FIG. 6, including diode saturation ballasted SiGedevices 58 a′, . . . , 58 n′ exhibiting velocity saturationcharacteristics according to the invention.

[0020]FIG. 7 illustrates a cross-sectional view of the SiGe Varactor(PIN) Diode structure 100 according to the invention.

[0021]FIG. 8 illustrates a cross-sectional view of the SiGe EpitaxialBase NPN 200 according to the invention.

[0022] FIGS. 9(a) and 9(b) illustrate cross-sectional views ofrespective SiGe Schottkey diode devices 300, 400, configured inaccordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0023] SiGe devices in a two terminal connection, such as thebase-collector diode configuration maintain a linear characteristic whenthe structure has a long base region. As the structure size decreases,the dynamic on-resistance of the device at high current decreases. Table1 below illustrates the SiGe npn transistor in a diode configuration(Base-Collector) with the linear resistance, the transition voltage ofvelocity saturation, the saturated resistance and the structure failurevoltage and failure current: TABLE 1 Transition Failure Failure TestMode Width Length R (Linear) Voltage R (saturated) Voltage CurrentBase-Collector 0.44 um 0.44 47.6 Ohms 4.5 V 180 Ohms 6.1 V 79 mA 0.8037.7 4.3 V 170 Ohms 6.3 120 1.50 20.4 4.2 V 160 Ohms 5.2 136 3.00 14.34.0 V 150 Ohms 5.5 220 6.00 8.02 3.8 V 140 Ohms 6.3 335 12.00 4.55 3.5 V 80 Ohms 5.9 510 47.6 1.45 None None 2.8 V 1.2 Amps

[0024] As shown in Table 1, the SiGe device in such a two terminalconnection, i.e., base-collector diode configuration, maintains a linearcharacteristic when the structure has a wide base region and, moreover,as the structure size decreases, the dynamic on-resistance of the deviceat high current decreases. The results of Table 1 further show that witha large SiGe npn, a low linear resistance structure may be obtained withno saturation phenomenon prior to failure. As the base length isdecreased to 12 μm, the onset of velocity saturation leads to atransition to a high resistance state that is significantly above thelinear resistance. The structure current does not increase leading theability to buffer off a voltage of 5.9 Volts at a failure current of 510mA. The voltage at which the velocity saturation occurs is about 3 Vacross the SiGe transistor.

[0025]FIG. 1 is a graph 90 depicting the current v. voltagecharacteristic of the diode-configured SiGe npn transistor (and varactoror PIN diode) at various device structure lengths. As shown in FIG. 1,SiGe npn transistor (and varactor or PIN diode) of longer lengths, e.g.,47 μm do not exhibit the velocity saturation effect as represented bythe line 92. As depicted in FIG. 1, a low linear resistance SiGe npntransistor (and varactor or PIN diode or npn base-collector junction)structure, e.g., at 12 μm in length, exhibits a linear resistance 94 atlow voltages and current and, exhibits diode velocity saturation 96. Atsome point along that line 96 the device will fail. As the length of theSiGe npn transistor (and varactor or PIN diode) structure decreases,e.g., below 12 μm in length such as represented by line 97, the currentcapability decreases, however, the device still exhibits diode velocitysaturation at lower currents as depicted at 98.

[0026] With greater specificity, to exploit this effect, in a firstembodiment, a SiGe npn (and in further embodiments, a p-i-n SiGe diode,and a SiGe varactor or SiGE Schottky) may be placed in a seriesconfiguration with peripheral receivers or drivers in such a manner toavoid electrothermal failure of the peripheral circuit. The element mayalso be divided into a plurality of SiGe transistors in parallel with aplurality of parallel I/O elements to provide the current distributionand velocity saturation effects. SiGe P-i-n diode and varactorstructures also demonstrate the collector saturation phenomenon and FIG.1 data demonstrates the transition from low to high resistance states.These structures also show a 10-20× increase in resistance as thestructures undergo saturation phenomenon. According to the invention,thus, a SiGe npn, varactor or p-i-n diode is configured in a seriesconfiguration with an I/O network device where the collector saturationis used advantageously to protect I/O circuitry. These elements can beplaced in a parallel configuration for current ballasting across all I/Olegs of the I/O network.

[0027] FIGS. 2-8 illustrate various circuit applications for theinventive SiGe structure which includes: the diode configured SiGevelocity saturation element, an SiGe p-i-n diode, SiGe varactor orSchottky diode, etc. The devices of FIGS. 2-8 include: 1) Receivernetworks: where an example embodiment is a SiGe in diode configurationin series with an emitter or base of a SiGe npn receiver; 2) I/O drivercircuits: where an example embodiment includes an SiGe npn in pull-downnetwork in series with the SiGe npn driver pull-down; and, 3) ESD powerclamps: where an example embodiment includes an output SiGe npn inseries with the ESD power clamp NFET or SiGe npn output clamp element.

[0028] As shown in FIG. 2, there is depicted an example differentialreceiver circuit 10 including diode saturation ballasted SiGe devices18, 19 according to the invention. The differential receiver circuit 10comprises first and second input pads 12, 13 connected to respectivetransistor devices 14, 15 in a differential receive configuration forreceiving input signals, with the emitter of each transistor device 14,15 connected in series with a respective diode configured SiGe diodesaturation element 18, 19 for providing overcurrent protection. FIG. 2Aillustrates another example embodiment of a differential receivercircuit 10′ including diode saturation ballasted SiGe device 18′exhibiting velocity saturation characteristics according to theinvention.

[0029]FIG. 3 illustrates an example Bipolar-based ESD power clamp 20with SiGe diode velocity saturation ballasting elements 28 a, . . . , 28n according to the invention. The ESD power clamp 20 includes an SiGenpn trigger device 22 which detects an overcurrent power supply Vddcondition and at such a condition, breaks down to provide base drive forone or more SiGe npn output clamp elements 24 a, . . . , 24 n which areconnected in series for effectively decreasing impedance between Vdd andground for providing chip overcurrent protection. The diode configuredSiGe saturation elements 28 a, . . . , 28 n provide resistor ballastingof the SiGe npn devices 24 a, . . . , 24 n.

[0030]FIG. 4 illustrates an example CMOS-based power clamp 30 withvelocity saturation diode ballasting elements 38 a, . . . , 38 n. TheCMOS-based power clamp 30 includes an RC discriminator circuit 32 whichprovides a device trigger according to the order of a time constantdetermined by resistor (R) and capacitor (C) elements that drive aplurality of NFET fingers (gates) 34 a, . . . , 34 n through an inverterdrive circuit 36 comprising one or more inverter devices 35. The powersupply Vdd of the device is connected to each of the NFET fingers 34 a,. . . , 34 n through a respective diode configured SiGe saturationelement (SiGe npn, SiGe p-i-n, varactor or Schottky) 38 a, . . . , 38 nfor providing current uniformity through each MOSFET 34A, . . . , 34 n.

[0031]FIG. 4A illustrates an example embodiment of a bi-polar powerclamp 30′ wherein the power supply Vdd of the device is connected toeach of the bi-polar device fingers 37 a, . . . , 37 n through therespective diode configured SiGe saturation element (SiGe npn, SiGep-i-n, varactor or Schottky) 38 a, . . . , 38 n for limiting current toground.

[0032]FIG. 5 illustrates an example receiver circuit 40 including diodesaturation ballasted SiGe devices 48 a, . . . , 48 n according to theinvention. The receiver circuit 40 comprises an input pad 42 connectedto plurality of respective transistor receive devices 44 a, . . . , 44 nconfigured to receive input signals, with the emitter of each transistordevice 44 a, . . . . , 44 n connected in series with a respective diodeconfigured SiGe diode saturation element (or SiGe varactor or p-i-n) 48a, . . . , 48 n for providing overcurrent protection. FIG. 5Aillustrates another example embodiment of a receiver circuit 40′including diode saturation ballasted SiGe devices 48 a′, . . . , 48 n′exhibiting velocity saturation characteristics according to theinvention.

[0033]FIG. 6 illustrates an example BiCMOS receiver circuit 50 includinga network of receiver devices 54 a, . . . , 54 n (e.g., npn SiGereceivers) each receiving signals from an input pad 52 through arespective current limiting SiGe heterojunction bipolar transistor (HBT)diode saturation ballast element 58 a, . . . , 58 n according to theinvention. FIG. 6A illustrates another example embodiment of a receivercircuit 50′ including diode saturation ballasted SiGe devices 58 a′, . .. , 58 n′ exhibiting velocity saturation characteristics according tothe invention.

[0034] Reference is now made to FIG. 7 which illustrates across-sectional view of the SiGe Varactor (or PIN) Diode structure 100according to the invention. Specifically, the SiGe Varactor (PIN) Diodestructure of FIG. 7 is formed from an npn transistor structure, andcomprises a semiconductor substrate 102, e.g., a p-type substrate, asub-collector layer 104 formed of N++ material (ion implanted) and twoshallow trench isolation regions (STI) 110 a, 110 b defining anepitaxial collector region 106 formed of N− material (epitaxially grownor ion implanted) and an intrinsic base region 108, e.g., formed ofsingle crystal SiGe p+ material formed between the isolation regionsabove the epitaxial collector 106. Further included is a low-temperatureepitaxy (LTE) PolySilicon Germanium extrinsic base region 112 formed byultra-high vacuum chemical vapor definition (UHV/CVD) process on top ofthe base region 108 in overlapping relation with each STI region 110 a,b. It is understood that the Ge concentration may be varied during thefilm deposition process to provide position-dependent SiGe alloy filmfor profile and device optimization of the base region. For instance,included in the LTE PolySilicon Germanium layer 112 is a doped epitaxialSiGe region 115 (e.g., p+ material) formed on top of the base region 108between the STI regions. A diode contact, e.g., mirrored metal contacts117 a, b, may be formed on top of the LTE SiGe layer 112 as showndisposed in alignment with respective STI region 110, b on each side ofrespective SiGe layer 112 facets 118 a,b. The varactor structure furthercomprises an N+ pedestal implant (reach-through) region 120 formedbetween the subcollector 104 and epitaxial collector 106 regions.Without the pedestal implant, the structure is referred to as a SiGep-i-n structure. This pedestal implant region is optional and may beformed in the varactor (FIG. 7) and a heterojunction bipolar transistor(HBT) device (for example as shown and described with respect to FIG. 8)for enhancing high-frequency SiGe npn device performance by increasingthe RF device cutoff frequency fT and providing a low-resistancecollector, and further increases collector-emitter breakdown voltage(BV_(CEO)) and improves velocity saturation effect to enhance ESDrobustness.

[0035]FIG. 8 illustrates a cross-sectional view of the SiGe EpitaxialBase NPN 200 according to the invention. Specifically, the SiGeEpitaxial Base NPN structure of FIG. 8 is an HBT device comprising asemiconductor substrate 202, e.g., a p-type substrate, a sub-collectorlayer 204 formed of N+ material (ion implanted) and two shallow trenchisolation regions (STI) 210 a, 210 b defining an epitaxial collectorregion 206. Further included is a low-temperature epitaxy (LTE)PolySilicon Germanium extrinsic base region 212 formed of p− dopantmaterial by UHV/CVD process on top of the base region 208 in overlappingrelation with each STI region 210 a, b. It is understood that the Geconcentration may be varied during the film deposition process toprovide position-dependent SiGe alloy film for profile and deviceoptimization of the base region. Further included are extrinsic baseimplant regions 215 a,b, e.g., p+ dopant material, extending into thecollector region 206 and abutting a respective STI region 210 a, b fordecreasing the extrinsic base resistance. According to conventionalprocessing steps, Silicon oxide 220 and Nitride film layers 224 areformed over the base region (LTE SiGe film) 212 and utilizing a mask, anemitter hole is etched therethrough to define an emitter window in theLTE SiGe film 212. It is through this emitter window that an N+ emitterdoped implant region 225 is formed. A final N+ doped polysilicon emitterfilm 230 is formed on top of the emitter region 225 overlaying siliconOxide and Nitride film layers 220, 224. Finally, emitter 240, base 250and collector contacts may be formed.

[0036]FIG. 9(a) illustrates a cross-sectional view of the SiGe-Schottkydiode configuration 300 which is similar to the P-I-N diode structure100 of FIG. 7 (i.e., without the pedestal implant structure) howeverincludes metal layer 315. Specifically, as shown in FIG. 9(a), the SiGeSchottky diode configuration includes a semiconductor substrate 302,e.g., a p-type substrate, a sub-collector layer 304 formed of N++material (ion implanted) and two shallow trench isolation regions (STI)310 a, 310 b defining an epitaxial collector region 306 formed of N−material (epitaxially grown or ion implanted) and an intrinsic baseregion 308 a, 308 b, e.g., formed of single crystal SiGe p+ material.Formed on top of this region is a Titanium Silicide metal layer 315 forconnection with contacts 317 a,b.

[0037]FIG. 9(b) illustrates a cross-sectional view of the SiGe Schottkydiode configuration 400 which is similar to the Schottky diodeconfiguration 300 of FIG. 9(a), however, further includes LTEPolySilicon Germanium extrinsic base region 412 a,b formed by UHV/CVDprocess. Particularly, SiGe Schottky device 400 includes a semiconductorsubstrate 402, e.g., a p-type substrate, a sub-collector layer 404formed of N++ material (ion implanted) and two shallow trench isolationregions (STI) 410 a, 410 b defining an epitaxial collector region 406formed of N− material and an intrinsic base region 408 a, 408 b, e.g.,formed of single crystal SiGe p+ material. In overlapping relation witheach region 412 a,b and intrinsic base region 408 a, 408 b, is aSilicide layer 415 (e.g., self-aligned or Salicide layer) according tothe invention.

[0038] The dopant concentrations for each of the devices illustrated inFIGS. 7, 8, and 9(a) and 9(b) are as follows: The emitter regions for aSiGe npn may include a concentration of dopants ranging anywhere between10¹⁹ cm⁻³ to 10²² cm⁻³, whereas the SiGe base region may include aconcentration of dopants ranging anywhere between 10¹⁷ cm³ to 10¹⁹ cm⁻³.It is understood that the concentration of Ge in the SiGe base regionmay be greater than 0% with peak values ranging anywhere between 5% and25%. The Ge profile formed may be of triangular, trapezoidal (plateaued)or rectangular shaped. For the collector regions, the dopantconcentration values may range anywhere between 10¹⁷ cm⁻³ (low dopantcollector region) to 10²¹ cm⁻³ (higher doped collector region)

[0039] While the invention has been particularly shown and describedwith respect to illustrative and preformed embodiments thereof, it willbe understood by those skilled in the art that the foregoing and otherchanges in form and details may be made therein without departing fromthe spirit and scope of the invention which should be limited only bythe scope of the appended claims.

Having thus described our invention, what we claim as new, and desire tosecure by Letters Patent is:
 1. An SiGe device configured to exhibithigh velocity saturation resistance characteristic for buffering largevoltages at low currents, wherein for circuit applications, said SiGedevice is connected in series with a circuit element for protection ofsaid circuit element.
 2. The SiGe device as claimed in claim 1,comprising as a heterojunction bipolar transistor (HBT) having acollector, a base and an emitter region, with said base beingelectronically connected to said emitter to thereby define a SiGebase-collector diode structure capable of exhibiting said high velocitysaturation resistance characteristic when voltage is applied.
 3. TheSiGe device as claimed in claim 1, comprising a collector and baseregion, each region selectively doped to form an SiGe diode deviceadapted to exhibit said high velocity saturation resistancecharacteristic.
 4. The SiGe device as claimed in claim 3, wherein saidcollector region of said SiGe diode device includes a selectively dopedpedestal implant region to form a SiGe varactor device adapted toexhibit said high velocity saturation resistance characteristic.
 5. TheSiGe device as claimed in claim 3, further comprising a metal layerinterfacing with said selectively doped base and collector regions toform an SiGe Schottky diode adapted to exhibit said high velocitysaturation resistance characteristic.
 6. The SiGe device as claimed inclaim 2, wherein a circuit application includes a receiver circuithaving a circuit element for receiving signals, said circuit elementconnected in series with said SiGe base-collector diode structure at abase terminal thereof.
 7. The SiGe device as claimed in claim 2, whereina circuit application includes a receiver circuit having a circuitelement for receiving signals, said circuit element connected in serieswith said SiGe base-collector diode structure at a collector terminalthereof.
 8. The SiGe device as claimed in claim 3, wherein a circuitapplication includes a receiver circuit having a circuit element forreceiving signals, said circuit element connected in series with saidSiGe varactor device structure at a base terminal thereof.
 9. The SiGedevice as claimed in claim 3, wherein a circuit application includes areceiver circuit having a circuit element for receiving signals, saidcircuit element connected in series with said SiGe varactor devicestructure at a collector terminal thereof.
 10. The SiGe device asclaimed in claim 6, wherein said receiver circuit includes adifferential receiver.
 11. The SiGe device as claimed in claim 9,wherein said receiver circuit includes a differential receiver.
 12. TheSiGe device as claimed in claim 2, wherein a circuit applicationincludes a power supply clamp circuit having one or more transistordevice output clamp elements connected with a voltage power supply, saidcircuit application further comprising said SiGe diode structure inseries connection between said power supply and said one terminal ofsaid transistor device output clamp element.
 13. The SiGe device asclaimed in claim 12, wherein a transistor device of said circuitapplication includes a CMOS-based FET device.
 14. The SiGe device asclaimed in claim 12, wherein a transistor device of said circuitapplication includes a bi-polar junction-based transistor device. 15.The SiGe device as claimed in claim 2, wherein a circuit applicationincludes a power supply clamp circuit having one or more transistordevice output clamp elements connected with a voltage power supply, saidcircuit application further comprising said SiGe base-collector diodestructure in series connection between a terminal of said transistordevice output clamp element and ground.
 16. The SiGe device as claimedin claim 2, wherein a circuit application includes a BiCMOS receivernetwork having a one or more SiGe bipolar transistor receiver devicesfor receiving an input signal, said circuit application furthercomprising said SiGe base-collector diode structure in series connectionwith a base input of each said one or more SiGe bipolar transistorreceiver devices.
 17. An SiGe device comprising: a semiconductorsubstrate of a first conductivity type; a doped collector region formedon top of said semiconductor substrate, said doped collector region ofsecond conductivity type; and, a base region of said first conductivitytype overlaying said doped collector region, wherein said device isconfigured to exhibit high velocity saturation resistance characteristicfor buffering large voltages at low currents.
 18. The SiGe device asclaimed in claim 17, wherein said doped collector region includes apedestal region comprising said second conductivity type material of aconcentration different from that of said doped collector region. 19.The SiGe device as claimed in claim 17, further including a polysilicongermanium layer of said first conductivity type formed overlaying saidsecond base region, said polysilicon germanium layer grown by lowtemperature epitaxy, said first conductivity type of a different dopingconcentration than said base region.
 20. The SiGe device as claimed inclaim 17, wherein said doped collector region includes sub-collectorlayer.
 21. The SiGe device as claimed in claim 17, further includingtrench isolation regions defining said base region and said dopedcollector region.
 22. An SiGe device comprising: a semiconductorsubstrate of a first conductivity type; a doped collector region formedon top of said semiconductor substrate, said doped collector region ofsecond conductivity type; a polysilicon germanium layer of said firstconductivity type forming a base region overlaying said doped collectorregion, said polysilicon germanium layer grown by low temperatureepitaxy, an dielectric film formed on said base region; and, apolysilicon germanium layer of said second conductivity type forming anemitter region overlaying said dielectric film in alignment with saidbase region, said doped polysilicon germanium layer of said firstconductivity type including an emitter region formed of said secondconductivity type in contact with said emitter layer, wherein said SiGedevice base region is electrically connected with said emitter baseregion, said collector and base regions forming a base-collector diode,said device being selectively doped to exhibit high velocity saturationresistance characteristic for buffering large voltages at low currents.23. The SiGe device as claimed in claim 22, wherein said collectorregion includes a pedestal region comprising said second conductivitytype material of a concentration different from that of said dopedcollector region for enhancing high-frequency SiGe npn deviceperformance by increasing the RF device cutoff frequency fT forhigh-frequency applications and improving velocity saturation effect.